128k x 8 static ram CY7C1018CV33 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05131 rev. *d revised august 3, 2006 features ? pin- and function-compatible with cy7c1018bv33 ?high speed ?t aa = 10 ns ? cmos for optimum speed/power ? center power/ground pinout ? data retention at 2.0v ? automatic power-down when deselected ? easy memory expansion with ce and oe options ? available in pb-free and non pb-free 300-mil-wide 32-pin soj functional description [1] the CY7C1018CV33 is a high-performance cmos static ram organized as 131,072 words by 8 bits. easy memory expansion is provided by an active low chip enable (ce ), an active low output enable (oe ), and tri-state drivers. this device has an automatic power-down feature that significantly reduces power consumption when deselected. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 16 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. the eight input/output pins (i/o 0 through i/o 7 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), or during a write operation (ce low, and we low). the CY7C1018CV33 is available in a standard 300-mil-wide soj. note: 1. for guidelines on sram system designs, please refer to the ?s ystem design guidelines? cypress application note, available on the internet at www.cypress.com. 14 15 logic block diagram pin configurations a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer power down we oe i/o 0 i/o 1 i/o 2 i/o 3 array i/o 7 i/o 6 i/o 5 i/o 4 a 0 a 11 a 13 a 12 a a 10 ce a a 16 a 9 1 2 3 4 5 6 7 8 9 10 11 14 19 20 24 23 22 21 25 28 27 26 top view soj 12 13 29 32 31 30 16 15 17 18 a 7 a 1 a 2 a 3 ce i/o 0 i/o 1 v cc a 13 a 16 a 15 oe i/o 7 i/o 6 a 12 a 11 a 10 a 9 i/o 2 a 0 a 4 a 5 a 6 i/o 4 v cc i/o 5 a 8 i/o 3 we v ss a 14 v ss 128k x 8
CY7C1018CV33 document #: 38-05131 rev. *d page 2 of 7 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage on v cc relative to gnd [2] ... ?0.5v to + 4.6v dc voltage applied to outputs [6] in high-z state .......................................?0.5v to v cc + 0.5v dc input voltage [2] .................................?0.5v to v cc + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... .............. .............. ...... > 2001v (per mil-std-883, method 3015) latch-up current..................................................... > 200 ma selection guide -10 -12 -15 unit maximum access time 10 12 15 ns maximum operating current comm?l 90 85 80 ma ind?l 85 ma maximum standby current 5 5 5 ma operating range range ambient temperature v cc commercial 0c to +70c 3.3v 10% industrial ?40c to +85c 3.3v 10% electrical characteristics over the operating range parameter description test conditions ?10 ?12 ?15 unit min. max. min. max. min. max. v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 0.4 v v ih input high voltage 2.0 v cc + 0.3 2.0 v cc + 0.3 2.0 v cc + 0.3 v v il input low voltage [2] ?0.3 0.8 ?0.3 0.8 ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ?1 +1 ?1 +1 a i oz output leakage current gnd < v i < v cc , output disabled ?1 +1 ?1 +1 ?1 +1 a i cc v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc comm?l 90 85 80 ma ind?l 85 ma i sb1 automatic ce power-down current ?ttl inputs max. v cc , ce > v ih v in > v ih or v in < v il , f = f max comm?l 15 15 15 ma ind?l 15 ma i sb2 automatic ce power-down current ?cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 comm?l 5 5 5 ma ind?l 5 ma capacitance [3] parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz, v cc = 3.3v 8pf c out output capacitance 8 pf notes: 2. v il (min.) = ?2.0v for pulse durations of less than 20 ns. 3. tested initially and after any design or process changes that may affect these parameters.
CY7C1018CV33 document #: 38-05131 rev. *d page 3 of 7 ac test loads and waveforms [4] switching characteristics over the operating range [5] parameter description -10 -12 -15 unit min. max. min. max. min. max. read cycle t rc read cycle time 10 12 15 ns t aa address to data valid 10 12 15 ns t oha data hold from address change 3 3 3 ns t ace ce low to data valid 10 12 15 ns t doe oe low to data valid 5 6 7 ns t lzoe oe low to low-z 0 0 0 ns t hzoe oe high to high-z [6, 7] 56 7 ns t lzce ce low to low-z [7] 33 3 ns t hzce ce high to high-z [6, 7] 56 7 ns t pu [8] ce low to power-up 0 0 0 ns t pd [8] ce high to power-down 10 12 15 ns write cycle [9, 10] t wc write cycle time 10 12 15 ns t sce ce low to write end 8 9 10 ns t aw address set-up to write end 8 9 10 ns t ha address hold from write end 0 0 0 ns t sa address set-up to write start 0 0 0 ns t pwe we pulse width 7 8 10 ns t sd data set-up to write end 5 6 8 ns t hd data hold from write end 0 0 0 ns t lzwe we high to low-z [7] 33 3 ns t hzwe we low to high-z [6, 7] 56 7 ns notes: 4. ac characteristics (except high-z) for all speeds are tested us ing the thvenin load shown in figure (a). high-z characterist ics are tested for all speeds using the test load shown in figure (c). 5. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v. 6. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in (d) of ac test loads. transition is measured 500 mv from steady-state voltage. 7. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 8. this parameter is guaranteed by design and is not tested. 9. the internal write time of the memory is defined by the overlap of ce low and we low. ce and we must be low to initiate a write, and the transition of any of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the signal t hat terminates the write. 10. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . 90% 10% 3.0v gnd 90% 10% all input pulses 3.3v output 30 pf (a) r 317 ? r2 351 ? rise time: 1 v/ns fall time: 1 v/ns (b) 3.3v output 5 pf (c) r 317 ? r2 351 ? high-z characteristics:
CY7C1018CV33 document #: 38-05131 rev. *d page 4 of 7 switching waveforms read cycle no. 1 [11, 12] read cycle no. 2 (oe controlled) [12, 13] write cycle no. 1 (ce controlled) [14, 15] notes: 11. device is continuously selected. oe , ce = v il . 12. we is high for read cycle. 13. address valid prior to or coincident with ce transition low. 14. data i/o is high impedance if oe = v ih . 15. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce icc isb impedance address data out v cc supply current t wc data valid t aw t sa t pwe t ha t hd t sd t sce t sce ce address we data i/o
CY7C1018CV33 document #: 38-05131 rev. *d page 5 of 7 write cycle no. 2 (we controlled, oe high during write) [14, 15] write cycle no. 3 (we controlled, oe low) [10, 15] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 16 data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 16 truth table ce oe we i/o 0 ?i/o 7 mode power h x x high-z power-down standby (i sb ) l l h data out read active (i cc ) l x l data in write active (i cc ) l h h high-z selected, outputs disabled active (i cc ) note: 16. during this period the i/os are in the output state and input signals should not be applied.
CY7C1018CV33 document #: 38-05131 rev. *d page 6 of 7 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package diagram all product and company names mentio ned in this document are the tradema rks of their respective holders. ordering information speed (ns) ordering code package diagram package type operating range 10 CY7C1018CV33-10vc 51-85041 32-lead 300-mil molded soj commercial 12 CY7C1018CV33-12vc 32-lead 300-mil molded soj commercial CY7C1018CV33-12vxi 32-lead 300-mil molded soj (pb-free) industrial 15 CY7C1018CV33-15vxc 32-lead 300-mil molded soj (pb-free) commercial 32-lead (300-mil) molded soj (51-85041) 51-85041-*a
CY7C1018CV33 document #: 38-05131 rev. *d page 7 of 7 document history page document title: CY7C1018CV33 128k x 8 static ram document number: 38-05131 rev. ecn no. issue date orig. of change description of change ** 109426 12/14/01 hgk new data sheet *a 113432 04/10/02 nsl ac test loads split based on speed *b 115046 05/30/02 hgk i cc and i sb1 modified *c 116476 09/16/02 cea add applications foot note on data sheet, pg 1 *d 493543 see ecn nxr added industrial operating range removed 8 ns speed bin from product offering changed the description of i ix from input load current to input leakage current in dc electrical characteristics table removed i os parameter from dc electrical characteristics table updated the ordering information table
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